The present invention relates generally to flash memory cell devices and more specifically, to improvements in planar charge trapping dielectric memory cell structures or improved alignment between lithography processes.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a xe2x80x9creadxe2x80x9d of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently a charge trapping dielectric memory cell structure that includes bit line oxides has been developed. FIG. 1a represents a cross section of a portion of a row of such charge trapping dielectric memory cells (e.g. cells 10a and 10b). The cells 10a and 10b are fabricated on a semiconductor substrate 12. Each cell 10 is characterized by a vertical stack of an insulating tunnel layer 14 a charge trapping dielectric layer 20a, 20b, and a top dielectric layer 22a, 22b formed over channel regions 24a, 24b of the substrate 12. Such stack may be referred to as an ONO stack because the insulating tunnel layer 14 and the top dielectric layer 22 are typically an oxide while the center charge trapping dielectric layer 20 is typically a nitride compound. The channel regions 24 are separated from each other, and defined by, bitline implants 18a, 18b, and 18c within the substrate 12. The ONO stacks are separated from each other, and defined by bit line oxide regions 16a, 16b, and 16c which are areas of the tunnel dielectric layer 14 above the bit line implants 18 that are thicker than the areas of the tunnel dielectric layer 14 that are over the channel regions 24.
Above the ONO stacks are a plurality of spaced apart polysilicon word lines 26 that are perpendicular to the bit line implants 18. Each word line is positioned above the top dielectric layer 22 of all cells within a row.
Similar to the floating gate device, the charge trapping dielectric memory cell 10 is programmed by inducing hot electron injection from the channel region 24 to the nitride layer 20 to create a non volatile negative charge within charge traps existing in the nitride layer 20. Again, hot electron injection can be achieved by applying a drain-to-source bias (e.g. bit line 18b to bit line 18a bias for programming cell 10a) along with a high positive voltage on the polysilicon word line 26 which forms a control gate over the cell 10a. The high voltage on the word line 26 inverts the channel region 24a while the drain-to-source bias accelerates electrons towards the drain bitline 18b. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region 24 and the tunnel oxide layer 14. While the electrons are accelerated towards the drain bitline 18b, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier.
Because the charge trapping layer 20 stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a charge storage region that is close to the drain region bit line to which the positive voltage was applied. As such, the charge trapping dielectric memory device can be used to store two bits of data, one near each of the bit lines of each cell.
The array is typically fabricated by first applying the ONO layer to the top surface of the substrate, etching back the ONO layer to the top surface of the substrate in the bit line regions, implanting the bit line regions, oxidizing the bit line regions to form the bit line oxides, and then applying the word lines to the top of the remaining ONO layer and the bit line oxides.
It should be appreciated that the height variations caused by the bit line oxides within the etched away portions of the ONO layer modulate reflected alignment illumination such that a lithography stepper may use an optical alignment system to properly align the various masks used during fabrication.
FIG. 1b represents a cross section of a portion of a row of charge trapping dielectric memory cells (e.g. cells 30a and 30b) with a planar structure. Cells 30a and 30b are fabricated on a semiconductor substrate 32. Positioned over the semiconductor substrate 32 is a vertical stack of an insulating tunnel layer 34 a charge trapping dielectric layer 38, and a top dielectric layer 40 positioned over the substrate 32.
Within the substrate are a plurality of parallel, and spaced apart, bit line implants 36a, 36b, and 36c which define a plurality of channel regions 44a, 44b, each of which is between adjacent bit line implants. Above the top dielectric layer 40 are a plurality of parallel, spaced apart, polysilicon word lines which are perpendicular to the bit line implants 36 and the channel regions 44. Each dielectric memory cell is defined by an intersection of a word line 42 and a channel region 44.
A recognized advantage of the planar structure shown in FIG. 1b over the bit line oxide structure depicted in FIG. 1a is that the planar structure provides a more precise pattern of the word lines and such precision permits scaling of structures to a smaller size. However, a recognized disadvantage of the planar structure is that there are no surface height variations that can be optically detected for aligning the word line pattern (and various other critical mask patterns) to the bit lines during the fabrication process.
Consequently, a need exists for a fabrication process for fabricating planar structure charge trapping dielectric memory cells that provides for facilitating mask alignment between the various masking steps.
A first aspect of the present invention is to provide a method of fabricating a planar architecture charge trapping dielectric memory cell array. The method comprises exposing a first photoresist to a first illumination pattern from a first lithography mask to pattern bit line regions in a core region of the wafer and to simultaneously pattern alignment mark regions on the wafer. Such first photoresist may be over a composite charge trapping dielectric layer on the surface of the wafer. The alignment mark regions may be in a scribe lane region of the wafer.
An impurity, such as arsenic, is simultaneously implanted into the wafer within the bit line regions and the alignment mark regions. The composite charge trapping dielectric layer is removed over the alignment mark regions and the wafer is exposed to an environment conducive to oxide growth. Within the alignment mark regions, the implant enhances oxidation of the wafer such that the grown oxide includes oxide protrusions within the alignment mark regions.
A layer of polysilicon may then be deposited over the surface of the wafer followed by a second photoresist. A second photoresist is exposed to a second illumination pattern from a second lithography mask to pattern word line regions within the core region of the wafer. Surface height variations of the oxide protrusions in the scribe lane region are used to detect alignment between the second mask and the first mask. The surface height variations of the oxide protrusions cause surface height variations of the overlying polysilicon layer and second photoresist.
Thereafter, additional processing steps, such as contact formation, may utilize the surface height variations of the overlying polysilicon layer to detect alignment between subsequent masks and the first mask. The polysilicon is a highly reflective material and causes a greater contrast in reflected alignment illumination such that alignment is easier to detect.
The composite charge trapping dielectric may comprises a tunnel dielectric layer, a charge trapping dielectric layer, and a top dielectric layer. As such, applying the charge trapping dielectric over the surface of the wafer may comprise: i) applying the tunnel dielectric layer on the surface of the wafer (the tunnel dielectric may be oxide such that it is grown on the surface); ii) applying the charge trapping dielectric layer on the surface of the tunnel dielectric layer; and iii) applying the top dielectric layer on the surface of the charge trapping dielectric layer.
A second method of fabricating a planar architecture charge trapping dielectric memory cell in accordance with the present invention may comprise: i) applying a tunnel dielectric layer on the surface of the wafer (the tunnel dielectric may be oxide such that it is grown on the surface); ii) applying the charge trapping dielectric layer on the surface of the tunnel dielectric layer; and iii) applying the top dielectric layer on the surface of the charge trapping dielectric layer.
Following application of the top dielectric layer, a first photoresist is applied over the surface of the top dielectric layer of the composite charge trapping dielectric. The first photoresist is then exposed to a first illumination pattern from a first mask to simultaneously pattern bit line regions in a core region of the semiconductor wafer and alignment mark regions. The alignment mark regions may be in a scribe lane region of the semiconductor wafer.
The first photo resist is etched to expose the composite charge trapping dielectric within the bit line regions and within the alignment mark regions and an impurity is implanted into the exposed bit line regions and the exposed alignment mark regions.
The first photoresist is removed and a protective mask is applied over the core region while the top dielectric layer within the alignment mark region is exposed. Each of the top dielectric layer, the charge trapping dielectric layer, and the tunnel dielectric layer may be removed in the exposed alignment mark regions to expose at least one of the semiconductor wafer and an oxide on the surface of the semiconductor wafer in the scribe lane region. The protective mask is removed and an oxide is then grown on the exposed alignment mark region to produce oxide protrusions within the alignment mark regions.
A layer of polysilicon is applied over the wafer including the core region. A second photoresist is applied over the surface of the layer of polysilicon and exposed to a second illumination pattern from a second mask to pattern word line regions within the core region. Surface height variations of the oxide protrusions are used to detect alignment between the second mask and the first mask. The surface height variations of the oxide protrusions cause surface height variations of the layer of polysilicon and the second photoresist. And, the step of exposing a second photoresist to a second illumination pattern from a second mask to pattern word line regions within the core region utilizes a reflected illumination pattern from the second photoresist caused by the oxide protrusions.
The layer of polysilicon may also be over the periphery region of the semiconductor wafer, the periphery region being positioned between the core region and the scribe lane region. And, the step of exposing a second photoresist to a second illumination pattern from a second mask to pattern word line regions further patterns transistor gates within the periphery region.
Thereafter, additional processing steps, such as contact formation, may utilize the surface height variations of the overlying polysilicon layer to detect alignment between subsequent masks and the first mask. The polysilicon is a highly reflective material and causes a greater contrast in reflected alignment illumination such that alignment is easier to detect.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings. The scope of the invention is set forth in the appended clams.